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NJU8714 NJU3555
STEREO BTL OUTPUTS SWITCHING DRIVER FOR Class D AMPLIFIER
GENERAL DESCRIPTION
The NJU8714 is a stereo BTL outputs switching driver for class D amplifier. It receives PWM/PDM signals from DSP outputs, and drives headphones or speakers by BTL outputs. Output drivers are composed of Series-Connected N-channel FETs, and output voltage levels can be controlled by variable power supply with keeping all of input signal information. The NJU8714 incorporates BTL outputs amplifiers, which eliminate AC coupling capacitors. Also, it provides "SEL" terminal which selects "Synchronous" or "Asynchronous". "Asynchronous" can be reduced the operating current. Therefore, it is suitable for portable audio set and others.
PACKAGE OUTLINE
NJU8714VB2
FEATURES
2-channel 1bit Audio Signal Input Stereo BTL Outputs Output Power : Typ.150mW@8 BEEP Function Standby Function Output Driver Control Function Operating Voltage VDD: 1.7V to 2.7V VDDO: 0V to 2.0V VG: 4.5V to 5.25V CMOS Technology Package Outline :SSOP20-B2
PIN CONFIGURATION
MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT1 VSSO OUT1X VDDO1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD SEL STBYB DIN2 VG OBEEP2 OUT2 VSSO OUT2X VDDO2
BLOCK DIAGRAM
VDD VSS VG VDDO1 DIN1
Level Shifter
OUT1
Control Logic Pre Driver
OUT1X
VSSO VDDO2 DIN2 MCK STBYB HALTB SEL BEEPIN OBEEP2
Level Shifter Level Shifter Level Shifter Level Shifter Level Shifter
OUT2
Control Logic Pre Driver
OUT2X
VSSO
OBEEP1
Ver.2004-05-21
-1-
NJU8714
TERMINAL DESCRIPTION
FUNCTION Master Clock Input Terminal Power GND: VSS=0V (Note.1) Output Driver Control Terminal 1bit Data Input Terminal 1 BEEP Signal Input Terminal BEEP Output terminal 1 Positive Output Terminal 1 Output GND terminal: VSS=0V (Note. 1) Negative Output 1 Output Power supply 1(Note. 2) Output Power supply 2(Note. 2) Negative Output 2 Positive Output Terminal 2 BEEP Output terminal 2 Pre-driver Power supply 1bit Data Input Terminal 2 Standby control terminal (L:Standby) Input Signal Synchronization With "MCK" 19 SEL I (H: Synchronous., L: Asynchronous.) 20 VDD Power Supply: VDD=2.5V (Note. 1) Pin No.2(VSS), 8(VSSO) and 13(VSSO) should be connected at the nearest point to the IC. (Note. 2) Pin No.10(VDDO1) and 11(VDDO2) should be connected at the nearest point to the IC. No. 1 2 3 4 5 6 7 8,13 9 10 11 12 14 15 16 17 18 SYMBOL MCK VSS HALTB DIN1 BEEPIN OBEEP1 OUT1 VSSO OUT1X VDDO1 VDDO2 OUT2X OUT2 OBEEP2 VG DIN2 STBYB I/O I I I I O O O O O O I I
INPUT TERMINAL STRUCTURE
VDD
Input Terminal
VSS
MCK, HALTB, DIN1, DIN2, BEEPIN, STBYB, SEL
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Ver.2004-05-21
NJU8714 NJU3555
FUNCTIONAL DESCRIPTION
(1) Signal Output The OUT1/1X and OUT2/2X generate respectively L-channel and R-channel output signals, which will be converted to analog signals via external 2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDO1 and VDDO2, which are the power supply for output drivers. To obtain better T.H.D. performance, the stabilization of the power is required. (2) Master Clock (MCK) Input 1-bit audio signals such as PWM or PDM to the DIN1 and DIN2 pins. By setting the SEL pin to "H", master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). In case of "SEL" = "L", input signals go into the amplifier circuits by own timing. Therefore, it requires careful design of PCB patterns from DSP to NJU8714. The setup time and the hold time should be kept in the AC characteristics because DIN1 and DIN2 are fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. (3) Power Supply VDD : Power supply for input part. VG : Power supply for control logic and pre-driver which drives the transistor gates of output drivers. It requires much higher power supply voltage than VDDO1 and VDDO2 for better T.H.D.. VDDO1, VDDO2 : Power supply for output drivers. (4) Output Control Output circuit is selected by the conditions of STBYB, HALTB, SEL, DIN1, DIN2 and MCK. STBYB L H L H HALTB L H H H SEL * * * L DIN1, DIN2 * * * L H L H MCK * * * * OUT1 VSSO Hi-z VSSO VDDO1 VSSO VDDO1 OUT2 VSSO Hi-z VSSO VDDO2 VSSO VDDO2 OUT1X VSSO Hi-z VDDO1 VSSO VDDO1 VSSO OUT2X VSSO Hi-z VDDO2 VSSO VDDO2 VSSO
*Don't care BEEP circuit is operated regardless of STBYB and HALTB. (5) Input Signal Synchronization Function DIN1 and DIN2 are synchronized with master clock by setting SEL pin to "H". By setting SEL pin to "L", DIN1 and DIN2 are asynchronous with master clock. (6) Output Driver Control Function By setting HALTB pin to "L", high side output drivers become OFF and Low side output drivers become ON, then both of OUT1/1X and OUT2/2X output VSSO level signals. This function works regardless of STBYB pin setting. (7) Standby Control Function By setting STBYB pin to "L", the NJU8714 becomes standby condition. During standby condition, by setting HALTB to "L", OUT1/1X and OUT2/2X become VSSO, and by setting HALTB pin to "H", OUT1/1X and OUT2/2X become Hi-z. To save the power supply current at standby, MCK requires "L" level.
Ver.2004-05-21
-3-
NJU8714
ABSOLUTE MAXIMUM RATINGS
(Ta=25C) PARAMETER Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation SYMBOL VDD VG VDDO Vin Topr Tstg PD RATING -0.3 to +2.75 VDD to +5.5 -0.3 to +5.5 -0.3 to VDD+0.3 -40 to +85 -40 to +125 450* UNIT V V C C mW
* : Mounted on two-layer board of based on the JEDEC. Note.1) All voltage values are specified as VSS=0V. Note.2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note.3) The relations of VDDO < VG must be maintained during operations.
ELECTRICAL CHARACTERISTICS
(Ta=25C, VDD=2.5V, VG=5.0V, VDDO1= VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, Load Impedance=32, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT VDD Supply Voltage VDDO1,2 Input Voltage VG Supply Voltage Output Driver High side Resistance Output Driver Low side Resistance Beep High side Resistance Power Supply Current At Standby Power Supply Current At Operating (Mute signal input) Input Voltage Input Leakage Current VDD VDDO VG RHPH OUT1, OUT1X, OUT2, OUT2X = VDDO1,2 - 0.1V VG=5.0V OUT1, OUT1X, OUT2, OUT2X = 0.1V VG= 5.0V OBEEP1, OBEEP2= VDD- 0.1V Stopping MCK, DIN1, DIN2, BEEPIN STBYB= 0V No-load operating, MCK= 256fS, DIN1, DIN2= 32fS, VDDO1= VDDO2= 0.18V MCK, DIN1, DIN2, BEEPIN, HALTB, STBYB, SEL 1.7 0 4.5 2.5 5.0 1.2 2.7 2.0 5.25 2 V
RHPL
-
1.2
2
RBEEPH IST IDD IDDO IG VIH VIL ILK
0.7VDD 0 -
9.0 0.05 0.25 1.0 -
15 1.0 0.1 0.5 2.0 VDD 0.3VDD 1.0
uA
mA V V uA
Note 1) High side resistance and low side resistance depend on VG and VDDO. Therefore, VG and VDDO should be adjusted on the application system. Note 2) Output power using 8 speaker is 150mW(TYP:THD+N=10%) at the following condition. VDD=2.5V, VG=5.0V, VDDO1= VDDO2=3.0V
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Ver.2004-05-21
NJU8714 NJU3555
TIMING CHARACTERISTICS
*
Audio Signal Input tMCKH MCK tMCKL
0.7VDD 0.3VDD
DIN1,DIN2 tDS tDH
0.7VDD 0.3VDD
(Ta=25C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT MCK Frequency MCK Pulse Width (H) MCK Pulse Width (L) DIN1,DIN2 Setup Time DIN1,DIN2 Hold Time BEEP Frequency fMCKI tMCKH tMCKL tDS tDH fb 8 9 9 5 5 0.1 35 20 MHz ns ns ns ns kHz
*
Output Control Signal Input
0.9VDD
BEEPIN, HALTB STBYB, SEL tUP tDN
0.1VDD
(Ta=25C, VDD=2.5V, VDDO1=VDDO2=1.7V, VSS=VSSO=0V, STBYB=HALTB=SEL=2.5V, fs=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Rise Time Fall Time tUP tDN 50 50 ns ns
Ver.2004-05-21
-5-
NJU8714
APPLICATION CIRCUIT
-Load Impedance: 32
MCK(1) HALTB(3) STBYB(18) SEL(19)
100uH 0.22uF 100uH
OUT1(7)
0.22uF
32 Speaker
OUT1X(9)
100uH 0.22uF 100uH 0.22uF
DIN1(4) DIN2(17)
10uF 2.2u
NJU8714
OUT2(14) 32 Speaker
OUT2X(12) VG(16) VDDO1(10) VSSO(8)
2.2uF 100uF
VG VDDO
VDD
VDD(20)
VSS(2) VDDO2(11) VSSO(13)
2.2uF 100uF 2.2uF 10uF
-Load Impedance: 8
22uH
MCK(1) HALTB(3) STBYB(18) SEL(19)
OUT1(7)
1.0uF 22uH 1.0uF
8 Speaker
OUT1X(9)
22uH 1.0uF 22uH 1.0uF
DIN1(4) DIN2(17)
10uF 2.2u
NJU8714
OUT2(14) 8 Speaker
OUT2X(12) VG(16) VDDO1(10) VSSO(8)
2.2uF 100uF
VG VDDO
VDD
VDD(20)
VSS(2) VDDO2(11) VSSO(13)
2.2uF 100uF 2.2uF 10uF
Note 3) De-coupling capacitors must be connected between each power supply pin and GND pin. Note 4) The power supply for VDDO requires fast driving response performance such as a switching regulator for T.H.D.. Note 5) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application.
-6-
Ver.2004-05-21
NJU8714 NJU3555
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2004-05-21
-7-

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